Engineering

Open Source Software: Timing Editor

I needed to draw a timing diagram for a mixed signal class I took.  I found 

The problem I was solving is shown below in the image.  It's rather tedious to figure out.  You have to remember that once a gate capacitance is charged up it ideally holds that charge until it is connected to again by either Vdd or Ground.

 

The gate turns out to be a falling edge triggered flip flop.  You can see it in the wikipedia:flip flop article that includes this diagram which was found after I did the timing diagram.

 

By Fudgy McFarlen, ago

1.2 Volt Band Gap Reference After the Start Up Circuit is fixed

Report Delivered for this project here

This entry records the steps taken after the above report was delivered.

BookSeeBookSee

TN3 was too long previous to this fix. Thus TN5 was not shutting off sufficiently and drawing too much current off of the current mirror.

Next Steps:

  • Redo startup transient analysisResearch Links
  • Redo Monte Carlo analysis including startup circuit
  • Go over the circuit for any possible reduction in sizes in the diodes and resistors.

 

Transient Analysis Redo Results

  • 1 to 1.8V supply voltage in 0.1 Volt steps.
  • About 0.5 mSec to turn on

Tweaking Monte Carlo V2 for output concavityResearch Links

 

Research 0L0inks

Tweaking Monte Carlo V2 for output concavity

 

 

 

Round Two Monte Carlo Results

Research Links

  • 968 in the desired working range
  • 32 versions exhibited in the bins: 47,62,93 mV

 

Preliminary Layout

  • The big rectangles are the diode connected bjt's
  • The little rectangles are the FETS
  • The long thin red lines are the resistors

FETs as Diodes

  • One way around the huge diodes would be to use nmos fets in weak inversion and diode connected.  Their characteristic is exponential under these circumstances and the worst case threshold voltage is 150mV less than the huge diode drop.  I am not sure if this is practical or not in actual practice but the simulation below looks good.
  • Resistor values had to be altered.  The large resistors can be reduced from around 12 MOhm down to about 3 MOhm.

  • The FET mismatch leads to the following Monte Carlo distribution.  Looks like I need to make the "diode" FETs bigger.

 

DIPDNW in the diode position

  • Appears to be 1/60 the area of the divpnp version

Monte Carlo Analysis @T=27 degrees C shows it well behaved more or less.  Still has issue with startup at times.

Monte Carlo Analysis @T=80 degrees C shows it well behaved.  Distribution at the low end it gone. 

 

Monte Carlo Analysis @T=0 degrees C shows markedly more false starts than higher temperatures

ac

 

By Fudgy McFarlen, ago

Agilent Application Note 1462 with ADS Design Files

Project Documentation and Files

Research Links

Files in Order of Usage in Application Note 1462

  • Step 2: Figure 3: FET_Gm_Calcs.sch
  • Step 3: Figure 5: FET_SP_NF_Match_Circ.sch
  • Step 4: Figure 7: Gain_and_Stab_DiscOpt.sch
  • Step 6: Figure 10: SP_NF_GainMatchK.sch
  • Step 7: Figure 12:  HB1Tone_LoadPullMagPh.sch
  • Step 8: HB1Tone_SourcePull.sch
  • Step 9: DA_LEMatch1_InputMatch1.sch

Once you have gone through the lower level blocks that make up the balanced amplifier the next step is to simulate the whole balanced amplifier subsystem.

BalancedLumpedAmp.sch

By Fudgy McFarlen, ago

MOSFET Extraction of Weak Inversion Parameters If: Normalization Current Vt Threshold Current N Body Factor Vp Pinchoff Voltage Lab Using Spice

 

This assignment was very difficult to finish because the lab had only one measurement device and the other teams were taking 3 to 4 days to figure out how to use it.  

Lab Assignment

If-Extraction   Threshold-Voltage-Extraction  Pinchoff-Voltage-Body-Factor

Brazil-Consulate-Stamp

 

By Fudgy McFarlen, ago

Low Voltage Schmitt Trigger Design in Weak Inversion Using LTSpice

The results of this project are probably wrong.  However SPICE and the Schmitt trigger circuit are all set up in the archive. If you find errors in the analysis or get better results somehow please come back and leave a comment detailing the error or linking out to your better analysis.

Low Voltage Schmitt Trigger Project Archive

Research Links

  • ECEN4827/5827 Analog IC Design – These notes from a course tell you how to set up a BSIM3v3 model and use in LTSpice circuit.  
  • Use of the NMOS symbol in LTSpice Local Copy – This link is from the page immediately previous link.  It has the specifics of using the library needed to use BSIM3v3
  • Introduction to LTSpice , Local Copy: MOSFET Device models used by SPICE (Simulation Program for Integrated Circuit Engineering) simulators can be divided into three classes: First Generation Models (Level 1, Level 2, Level 3 Models), Second Generation Models (BISM, HSPICE Level 28, BSIM2) and Third Generation Models (BSIM3, Level 7, Level 8, Level 49, etc.) The newer generations can do a better job with short channel effects, local stress, transistors operating in the sub-threshold region, gate leakage (tunneling), noise calculations, temperature variations and the equations used are better with respect to convergence during circuit simulation. In general first generation models are recommended for MOSFETs with gate lengths of 10um or more. If not specified most SPICE MOSFET Models default to level=1 (Shichman and Hodges) 
  • BSIM3v3.2.2 MOSFET Model ( Appears to be "the manual" )  
  • BSIM3 Archive – files can be downloaded here.  However at one point in the LTSPICE documents above they mentioned the MOSFET model or library was modified for usage with LTSPICE.  I do not know how much modification was required.
  • LTSPICE – Adding components.  

References

Notes

  • I have verified that the model works below mosfet threshold voltage by simulating an inverter at 0.300 Volts supply voltage. 
  • Transistor circuits become very slow as you lower their current.  Perhaps that is why I think so slowly.  I am guessing my neurological system is pretty low voltage.

Additional Links

By Fudgy McFarlen, ago