I needed to draw a timing diagram for a mixed signal class I took. I found
The problem I was solving is shown below in the image. It's rather tedious to figure out. You have to remember that once a gate capacitance is charged up it ideally holds that charge until it is connected to again by either Vdd or Ground.
The gate turns out to be a falling edge triggered flip flop. You can see it in the wikipedia:flip flop article that includes this diagram which was found after I did the timing diagram.
- An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic
- A LOW POWER PRESCALER, PHASE FREQUENCY DETECTOR, AND CHARGE PUMP FOR A 12 GHZ FREQUENCY SYNTHESIZER has a basic cml gate
- A Dynamic-Logic Frequency Divider for 5-GHz WLAN Frequency Synthesizer
- Design of MOS Current-Mode Logic Standard Cells Technology: NSC 0.18 µm CMOS9
- High-Speed CMOS Dual-Modulus Prescalers for Frequency Synthesis by Ranganathan Desikachari
- NEW CML LATCH STRUCTURE FOR HIGH SPEED PRESCALER DESIGN
- A 3.8-mW 2.5-GHz Dual-Modulus Prescaler in a 0.8 µm Silicon Bipolar Production Technology
- Measuring the speed of light
- Optical gyro – relativity
- Build a Fiber Optic Gyro Sagnac's paper
- Optical Gates – this is too close to the edge
- Trillionth of Second Camera
- Single Photon Detector of any type
- Single / Double slit experiment with LED / Laser
- Polarized light – LED
- Stress analyzer – birefringence
- Particle manipulation with laser beams – demonstrate forces with light
- demostrate cooling with light
- entangled photons generator
- gravity effect on speed of light / wavelength
- some sort of super accurate clock based on opto electronics
- Transmit audio with a laser pen
- Measure speed of light with a laser
- 3D object measurement tool for shipping estimate etc.
- Raman Spectrometer
Speed of Light Measurement
- Speed of Light with a laser pointer / diode
- Infrared Thermometer assembly
- SENSOR DE LASER PARA MEDIÇÃO DA VELOCIDADE DA LUZ
2 Color Optical Pyrometer
This entry records the steps taken after the above report was delivered.
TN3 was too long previous to this fix. Thus TN5 was not shutting off sufficiently and drawing too much current off of the current mirror.
Redo startup transient analysisResearch Links
- Redo Monte Carlo analysis including startup circuit
- Go over the circuit for any possible reduction in sizes in the diodes and resistors.
Transient Analysis Redo Results
- 1 to 1.8V supply voltage in 0.1 Volt steps.
- About 0.5 mSec to turn on
Tweaking Monte Carlo V2 for output concavityResearch Links
Tweaking Monte Carlo V2 for output concavity
Research LinksResearch LinksResearch Links
Round Two Monte Carlo Results
- 968 in the desired working range
- 32 versions exhibited in the bins: 47,62,93 mV
- The big rectangles are the diode connected bjt's
- The little rectangles are the FETS
- The long thin red lines are the resistors
FETs as Diodes
- One way around the huge diodes would be to use nmos fets in weak inversion and diode connected. Their characteristic is exponential under these circumstances and the worst case threshold voltage is 150mV less than the huge diode drop. I am not sure if this is practical or not in actual practice but the simulation below looks good.
- Resistor values had to be altered. The large resistors can be reduced from around 12 MOhm down to about 3 MOhm.
- The FET mismatch leads to the following Monte Carlo distribution. Looks like I need to make the "diode" FETs bigger.
DIPDNW in the diode position
- Appears to be 1/60 the area of the divpnp version
Monte Carlo Analysis @T=27 degrees C shows it well behaved more or less. Still has issue with startup at times.
Monte Carlo Analysis @T=80 degrees C shows it well behaved. Distribution at the low end it gone.
Monte Carlo Analysis @T=0 degrees C shows markedly more false starts than higher temperatures