Setting LTspice up for use with Electric

Research Links

LTspice is provided courtesy of Linear Technology, Inc. and authored by Mike Engelhardt. Possible contact for topo.

Extraction of MOSFET Parameters Lab using 4007 Array

Lab Document: Extraction of MOSFET Parameters using 4007 Array

My PDF Solution – Warning Will Robinson:  I never get 100% correct!

The following two measurements are where the MOSFET is in saturation and use the 8if method to nd ISpecific. In this
case because we are looking into the MOSFET source circuit we do not have to worry about slope factor n: Simply go to the
point where gms/ID=20 and read o the current the divide by 8 to arrive at the specic current.

Part_01_Vg_2_Vd_5  Part_1_Source_Drive

Vgate = 2:0 VD = 5 : Ispecific = 0:735 uAmp

Part_01_Vg_1p7_Vds_5V  Part_1_Source_Drive

Vgate = 1:7 Nominal Vt VD = 5 : ISpecific = 0:92 uAmp

The triode region determination of specic current is a little more complicated. I used Vds=15mVolts which results in if = 3
and ir = 2 which is convenient in the last part of the calculation of specic current.

Part_01_Vg_2_Vds_p015  Part_1_Source_Drive

Part_01_Vg_1p7_Vds_p015  Part_1_Source_Drive

Unabiguous-Extraction-Vt_If  UnAmbiguous-Parameter-Circuit

Vt_vs_Vs  n_vs_Vs       

1.2 Volt Band Gap Reference After the Start Up Circuit is fixed

Report Delivered for this project here

This entry records the steps taken after the above report was delivered.

BookSeeBookSee

TN3 was too long previous to this fix. Thus TN5 was not shutting off sufficiently and drawing too much current off of the current mirror.

Next Steps:

  • Redo startup transient analysisResearch Links
  • Redo Monte Carlo analysis including startup circuit
  • Go over the circuit for any possible reduction in sizes in the diodes and resistors.

 

Transient Analysis Redo Results

  • 1 to 1.8V supply voltage in 0.1 Volt steps.
  • About 0.5 mSec to turn on

Tweaking Monte Carlo V2 for output concavityResearch Links

 

Research 0L0inks

Tweaking Monte Carlo V2 for output concavity

 

 

 

Round Two Monte Carlo Results

Research Links

  • 968 in the desired working range
  • 32 versions exhibited in the bins: 47,62,93 mV

 

Preliminary Layout

  • The big rectangles are the diode connected bjt's
  • The little rectangles are the FETS
  • The long thin red lines are the resistors

FETs as Diodes

  • One way around the huge diodes would be to use nmos fets in weak inversion and diode connected.  Their characteristic is exponential under these circumstances and the worst case threshold voltage is 150mV less than the huge diode drop.  I am not sure if this is practical or not in actual practice but the simulation below looks good.
  • Resistor values had to be altered.  The large resistors can be reduced from around 12 MOhm down to about 3 MOhm.

  • The FET mismatch leads to the following Monte Carlo distribution.  Looks like I need to make the "diode" FETs bigger.

 

DIPDNW in the diode position

  • Appears to be 1/60 the area of the divpnp version

Monte Carlo Analysis @T=27 degrees C shows it well behaved more or less.  Still has issue with startup at times.

Monte Carlo Analysis @T=80 degrees C shows it well behaved.  Distribution at the low end it gone. 

 

Monte Carlo Analysis @T=0 degrees C shows markedly more false starts than higher temperatures

ac

 

Low Voltage Schmitt Trigger Design in Weak Inversion Using LTSpice

The results of this project are probably wrong.  However SPICE and the Schmitt trigger circuit are all set up in the archive. If you find errors in the analysis or get better results somehow please come back and leave a comment detailing the error or linking out to your better analysis.

Low Voltage Schmitt Trigger Project Archive

Research Links

  • ECEN4827/5827 Analog IC Design – These notes from a course tell you how to set up a BSIM3v3 model and use in LTSpice circuit.  
  • Use of the NMOS symbol in LTSpice Local Copy – This link is from the page immediately previous link.  It has the specifics of using the library needed to use BSIM3v3
  • Introduction to LTSpice , Local Copy: MOSFET Device models used by SPICE (Simulation Program for Integrated Circuit Engineering) simulators can be divided into three classes: First Generation Models (Level 1, Level 2, Level 3 Models), Second Generation Models (BISM, HSPICE Level 28, BSIM2) and Third Generation Models (BSIM3, Level 7, Level 8, Level 49, etc.) The newer generations can do a better job with short channel effects, local stress, transistors operating in the sub-threshold region, gate leakage (tunneling), noise calculations, temperature variations and the equations used are better with respect to convergence during circuit simulation. In general first generation models are recommended for MOSFETs with gate lengths of 10um or more. If not specified most SPICE MOSFET Models default to level=1 (Shichman and Hodges) 
  • BSIM3v3.2.2 MOSFET Model ( Appears to be "the manual" )  
  • BSIM3 Archive – files can be downloaded here.  However at one point in the LTSPICE documents above they mentioned the MOSFET model or library was modified for usage with LTSPICE.  I do not know how much modification was required.
  • LTSPICE – Adding components.  

References

Notes

  • I have verified that the model works below mosfet threshold voltage by simulating an inverter at 0.300 Volts supply voltage. 
  • Transistor circuits become very slow as you lower their current.  Perhaps that is why I think so slowly.  I am guessing my neurological system is pretty low voltage.

Additional Links