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Project Report: Please note I ran out of time so the organization and writing of this report is lacking. It does cover the basics of designing an 8/9 dual modulus prescaler. |
If you improve upon this report please come back to this post and put a link to your improved version in the comments.
Research Links: CML Prescaler
- An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic
- A LOW POWER PRESCALER, PHASE FREQUENCY DETECTOR, AND CHARGE PUMP FOR A 12 GHZ FREQUENCY SYNTHESIZER – Evan Lee Eschenko – has a basic cml gate
- A Dynamic-Logic Frequency Divider for 5-GHz WLAN Frequency Synthesizer
- Design of MOS Current-Mode Logic Standard Cells Technology: NSC 0.18 µm CMOS9
- High-Speed CMOS Dual-Modulus Prescalers for Frequency Synthesis by Ranganathan Desikachari
- NEW CML LATCH STRUCTURE FOR HIGH SPEED PRESCALER DESIGN
- A 3.8-mW 2.5-GHz Dual-Modulus Prescaler in a 0.8 µm Silicon Bipolar Production Technology
- ECEN620: Network Theory Broadband Circuit Design
- High Speed Communication Circuits and Systems – Lecture 14 – High Speed Frequency Dividers
- Design of a 5.8 GHz Multi-Modulus Prescaler – Good discussion of how multi modulus prescaler works – block level state machine
- Frequency Dividers – Jri Lee
- Generalized Multi Modulus Dividers using 2/3 cells
- A 1.8V, 3GHz 16/17 Dual Modulus Prescaler in 0.35µm CMOS Technology – has merged Nand D Flip Flop, D Flip Flop and Merged 3-input AND & NAND D-FF topologies for the architecture realization
- A New Dual-Modulus Divider Circuit Technique – I like the way he draws the CML logic block diagrams
Research Links: CML to CMOS converter circuit
This lecture talks about how you need a level shifter for transistor inputs lower on the input ladder of CML logic.
Support Links
- lecture7 – Current mode logic – MUX, XOR, Latch
- lecture8 – Current mode logic – Latch design
- IIT Video Lectures on VLSI Broadband Communication Circuits by Prof. Nagendra Krishnapura
- 74HC193 presettable up / down counter LTSPICE files
- Binary Counter
- Avant HSPICE – Performing Behavoiral Modeling – The entire book
- A Digital Frequency Synthesizer Using Phase Locked Loop Technique – Gursharan Reehal
- Pulse swallowing frequency divider with low power and compact structure Has TSPC registers
- High Speed Communication Circuits and Systems – Lecture 14 – High Speed Frequency Dividers
Additional Links
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