Useful Thoughts and Actions Taken

Low Voltage Schmitt Trigger Design in Weak Inversion Using LTSpice

The results of this project are probably wrong.  However SPICE and the Schmitt trigger circuit are all set up in the archive. If you find errors in the analysis or get better results somehow please come back and leave a comment detailing the error or linking out to your better analysis.

Low Voltage Schmitt Trigger Project Archive

Research Links

  • ECEN4827/5827 Analog IC Design – These notes from a course tell you how to set up a BSIM3v3 model and use in LTSpice circuit.  
  • Use of the NMOS symbol in LTSpice Local Copy – This link is from the page immediately previous link.  It has the specifics of using the library needed to use BSIM3v3
  • Introduction to LTSpice , Local Copy: MOSFET Device models used by SPICE (Simulation Program for Integrated Circuit Engineering) simulators can be divided into three classes: First Generation Models (Level 1, Level 2, Level 3 Models), Second Generation Models (BISM, HSPICE Level 28, BSIM2) and Third Generation Models (BSIM3, Level 7, Level 8, Level 49, etc.) The newer generations can do a better job with short channel effects, local stress, transistors operating in the sub-threshold region, gate leakage (tunneling), noise calculations, temperature variations and the equations used are better with respect to convergence during circuit simulation. In general first generation models are recommended for MOSFETs with gate lengths of 10um or more. If not specified most SPICE MOSFET Models default to level=1 (Shichman and Hodges) 
  • BSIM3v3.2.2 MOSFET Model ( Appears to be "the manual" )  
  • BSIM3 Archive – files can be downloaded here.  However at one point in the LTSPICE documents above they mentioned the MOSFET model or library was modified for usage with LTSPICE.  I do not know how much modification was required.
  • LTSPICE – Adding components.  

References

Notes

  • I have verified that the model works below mosfet threshold voltage by simulating an inverter at 0.300 Volts supply voltage. 
  • Transistor circuits become very slow as you lower their current.  Perhaps that is why I think so slowly.  I am guessing my neurological system is pretty low voltage.

Additional Links

By Fudgy McFarlen, ago

CI Brasil – CT1 Porto Alegre Inscription Open

Calendário CT1

  • 17/04/14         Início da Fase 1 – Abertura das inscrições
  • 22/06/14         Fim da Fase 1 – Fechamento das inscrições. 
  • 26/06/14         Início da Fase 2 – Prova online
  • 04/07/14         Fim da Fase 2 – Divulgação dos selecionados
  • 04/07/14         Início da Fase 3 – Início do envio de documentos
  • 18/07/14         Fim da Fase 3 – Último dia para envio da documentação POR SEDEX (data de postagem).
  • 12/07/14         Divulgação de vagas remanescentes
  • 04/08/13         Matrícula presencial
  • 05/08/14         Cerimônia de Abertura e Orientation Day (manhã)………..Início do Programa de Formação (tarde).
  • 31/07/15         Fim do Programa de Formação
By Fudgy McFarlen, ago

Book Review: Professor Van Nostrand: CMOS Analog Design Using All Region MOSFET Modeling

Research Links

The class taught by the author is centered around the ability to scale MOSFET's across technologies using normalization.   This is typified by the second question on the test given in the course.   

Test Page 2

Partial solution of question 2 – This solution derives part A & B W/L.  Part C is just plug and chug.

Laboratory where parameters are extracted using SPICE

By Fudgy McFarlen, ago