Monte Carlo Analysis with Cadence and the XFAB Design Kit
Getting Monte Carlo analysis to work on Cadence can be a bit of a puzzle given how Cadence is a ball of various software tools stuck together with spit. You have have seen the following intermodal nastygram:
Research Links
Book: CMOS: Jacob Baker
Jacob Baker maintains CMOSedu.com. There is a large amount of useful material there.
Research Links
- CMOS Circuit Design, Layout, and Simulation, Third Edition – there are files on that page for use with LTSPICE , Cadence etc
- Setting up ELECTRIC to work with LTSPICE
- VLSI and ASIC Technology Standard Cell Library Design
- The Designers Guide
PLL Phase Lock Loop Design and Modeling
Links
- Phase Locked Loop Simulation using T-Spice
- SPICE PLL file There is one error found in the code when I copy it from the pdf In the statement of NMOS /PMOS Model,VTO(letter "O") is spelled into VT0(zero) .that's wrong
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- Inset photo example can be found on the Nap0 page. It uses his LTSPICE "control" library. Click on image. My notes are on this page
Pulse Generation and Signal Conditioning Circuits
Research Links
Pulse Generation Circuits
- Dual edge delay
- Leading edge delay
- Trailing edge delay
- Dual edge detector / frequency doubler
- Leading edge detector
- Trailing edge detector
Level shifter with low quiescent current
Research Links
A slightly different implementation:
Charge Pump Articles – No Inductors Allowed
XFAB Links
- FeatureXplorer
- Summary Sheet: 0.18 μm Process Family: XH018 0.18 Micron Mixed-Signal HV CMOS Technology
- 0.18 μm Process Family: XH018 0.18 Micron Modular Analog Mixed HV Technology
- Ambient Light Sensing Made Easy with X-FAB – has photo diode side profiles
- XHB06 Photo Diode Evaluation Chips – See image below for cross sections:
XFAB has integrated photo diodes in the XH018 process. However it was difficult to find the scaling factor for the light input pin on the photo diode schematic symbol. The only place I have found it thus far is in the photo diode model:
The photodiode light input is a third terminal on the diode symbol. In order to do a simulation one must know how light intensity scales to light input terminal voltage. This information was discovered in the comments one of the photodiode library files.
Excerpt from file: dphoa.scs
* TERMINALS: anode=PSUB, cathode=DNWELL, lpower=lpower[1uV==1uW]
* VARIABLES: area[m2], perimeter[m], wavelength[1==1um]
* TNOM = 27 deg C; TEMP=27 deg C
Paper Links
- On the Feasability of Indoor Light Energy Harvesting for Wireless Sensor Networks
- Analysis-Design-Implementation-Integrated-High-Performance-Charge-Pumps
- Charge_Pump_Intro
- Efficiency-Comparison-between-Doubler-and-Dickson-Charge-Pumps
A 0.35 um CMOS Solar Energy Scavenger with Power Storage Management System
Cross couple voltage doubler.
Design of Very Low Voltage CMOS Rectifier Circuits – Bulk connection is very important in voltage multipliers. In a Dickson charge pump DTMOS connection is the one that works best. That assumes you are using isolated transistors so you do not end up with elevated theshold voltages.
Dickson model above simulates the action of the main line of the voltage multiplier but does not cover the power required by the clock inverters that drive the 2 phases. Thus it does not apply for over all efficiency calculations.
The current of the 5V section of the level shifter is too high for very low consumption circuits. My simulations had it at 10uAmp @ 1MHz.
This charge recycling scheme does not work if the stray capacitance is negligible compared to the pump capacitance. My lack of understanding lead me to try using it with my test design simulations. When no difference in current consumption showed up I had to scatch my head.
- Power Efficiency Optimization of Fully Integrated Dickson Charge Pumps
- Inductorless Converter Energy Harvesting 1.2µW BGR
Voltage Regulation for Energy Scavenging
Circuit Implementation Notes
- Area Efficiency Improvment of CMOS Charge Pumps: If p is the ratio of stray capacitance to desired capacitance (Cp p Ca) and is determined by the type of capacitors used. For double poly capacitors, this value is usually between 10 and 20 percent. Thin oxide MOS capacitors provide 5-15% stray capacitance, with a higher capacitance per unit area than double poly capacitors. For poly-metal capacitors, p can be as much as 20-50%.


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